METHOD AND DEVICE FOR CHECKING THE CONTROL SIGNALS DERIVED FROM AN INSTRUCTION OF AN ELECTRONIC DATA PROCESSING UNIT

1. Method for an electronic data processing system for checking the control signals derived from an instruction, wherein a check value is formed from these control signals which are combined with time clock signals according to a logic function, and this check value is compared with a desired check value associated with the instruction and denoting correct control signals, and wherein, in the event of a mismatch of the check value and the desired check value, an error signal is generated, characterized by the following method steps : a) for checking whether the control signals (ATI to ZTI ) associated with the cycle times (TO to TL) of an instruction occur at the proper times, control signals (ATO to ZTO ) and an arbitrarily selectable fed back initial logic signal (aA) are combined according to an arbitrarily selectable logic function (f) in a logic circuit (107) in an initial step (i=0), forming a logic signal (aO) ; b) during the same cycle time (TO), the logic signal (aO) is temporarily stored in a first storage element (101) at a first clock time (A-clock) ; c) during the same cycle time (TO), the logic signal (aO) is transferred at a second clock time (B-clock) from the first storage element to a second storage element (104), whence it is fed back to the input of the logic circuit ; d) during the respective subsequent cycle times up to the penultimate cycle time (T1 to TL-1), the respective subsequent control signals (AT1 to ZT1 , ... ATL-1 to ZTL-1 ) and the logic signal, formed in the respective preceding cycle time within the validity slot of the first cycle time (TO) to the antepenultimate cycle time (TL-2) of a logic instruction and fed back to the input of the logic circuit, are combined with each other according to the logic function (f) within the validity slot of the first (aO) to the penultimate (aL-2) logic signal, forming a logic signal (a1 to aL-1) ; e) during the respective subsequent cycle time up to the penultimate cycle time (T1 to TL-1), the respective subsequent signals (a1 to aL-1) are temporarily stored in the first storage element at the respective first clock time ; f) during the respective subsequent cycle time up to the penultimate cycle time (T1 to TL-1), the respective subsequent logic signals (a1 to aL-1) are transferred at the respective second clock time from the first storage element to the second storage element, whence they are fed back to the input of the logic circuit ; g) during the last cycle time (TL) of an instr