OPDELING AF SOC-ARKITEKTUR

The present disclosure provides an apparatus comprising a package assembly that includes a first base chiplet, a first logic chiplet stacked on the first base chiplet, a first interconnect structure to couple the cluster of compute units to the first interconnect fabric, a second base chiplet couple...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	Cheney, Lance, Teshome, Melaku, Matam, Naveen, Koker, Altug, Xavier, Binoj, Jahagirdar, Sanjeev, Finley, Eric, Mastronarde, Josh, George, Varghese, Striramassarma, Lakshminarayanan, Rajwani, Iqbal, Vemulapalli, Vikranth
Format:	Patent
Sprache:	dan
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	The present disclosure provides an apparatus comprising a package assembly that includes a first base chiplet, a first logic chiplet stacked on the first base chiplet, a first interconnect structure to couple the cluster of compute units to the first interconnect fabric, a second base chiplet coupled to the first base chiplet by a second interconnect structure, a second logic chiplet stacked on the second base chiplet, and a third interconnect structure to couple the second logic chiplet to the second interconnect fabric. In the provided apparatus, the first logic chiplet is manufactured using a different process technology than that used to manufacture the first and second base chiplets.