JITTERARMES PLL-TAKTRÜCKGEWINNUNGSSYSTEM HOHER PHASENAUFLÖSUNG

A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO (14) is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX (22), prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit (26). Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.