Herstellungsverfahren für eine mit eingebetteten passiven Dünnschichtbauteilen versehene mehrschichtige Leiterplatine

The specification describes of multilevel printed circuit boards and a process for their manufacture in which capacitors and other passive components are buried between levels of the multilevel board. The capacitor in the multilevel structure is designed so that access is conveniently provided to co...

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Bibliographische Detailangaben
Hauptverfasser:	MANZIONE, LOUIS THOMAS, KOLA, RATNAJI RAO, WATTS, RODERICK KENT
Format:	Patent
Sprache:	ger
Schlagworte:	BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY LAYERED PRODUCTS LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PERFORMING OPERATIONS PRINTED CIRCUITS SEMICONDUCTOR DEVICES TRANSPORTING
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Beschreibung
Zusammenfassung:	The specification describes of multilevel printed circuit boards and a process for their manufacture in which capacitors and other passive components are buried between levels of the multilevel board. The capacitor in the multilevel structure is designed so that access is conveniently provided to connect from the parallel plate electrodes of the interlevel capacitor to the board surface or to another board level using plated through hole interconnects.