Burstmodus-Halbleiterspeicheranordnung

In a semiconductor memory device having a burst function, a memory circuit (2) inputs and outputs information corresponding to an external input signal (A1-A10) in synchronization with an internal clock signal (S4). A burst operation control circuit receives an external reference clock signal (CX) and an enable signal (E1) for switching a burst operation mode and a stand-by mode, so as to suspend supplying of the external input signal in the burst operation mode and suspend generation of the first internal clock signal in the stand-by mode.