Pilot-Transistor für quasi-vertikale DMOS-Anordnung

An isolated pilot transistor 100 for a QVDMOS device 10 has a gate and drain region in symmetry with the sources 20 of device 10 and an additional resistance 116 in the drain 118 to compensate for current spreading between the source 120 and the buried layer resistor 132.

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Bibliographische Detailangaben
1. Verfasser: PEARCE, LAWRENCE G
Format: Patent
Sprache:ger
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Beschreibung
Zusammenfassung:An isolated pilot transistor 100 for a QVDMOS device 10 has a gate and drain region in symmetry with the sources 20 of device 10 and an additional resistance 116 in the drain 118 to compensate for current spreading between the source 120 and the buried layer resistor 132.