Hochleistungs-Sperrschichttransistor mit niedriger Schwellenspannung

Low threshold voltage MOS devices having buried electrodes (46) are disclosed herein. Such devices have source and drain regions which include tip regions (36A, 38A) and plug regions (36, 38). The buried electrodes (46) have bottom boundaries located above the bottoms of the plug regions (36, 38). The buried electrode (46) has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. The exact dopant concentrations and locations of the buried electrodes (46) should be provided such that punch through is avoided in MOS devices.