Verfahren zur Herstellung von Sacklöchern und hergestellte Struktur

A first metal region (12,14) is formed over an underlying region (10). A first insulating layer (16) is formed over the integrated circuit. A second insulating layer (18) is then formed over the first insulating layer (16). A portion of the second insulating (18) layer is etched to expose a portion of the first insulating layer (16) wherein the exposed first insulating layer (16) and the remaining second insulating layer (18) form a substantially planar surface. A metal oxide layer (20) is formed over the exposed first insulating layer (16) and the remaining second insulating layer (18). A photoresist layer (22) is formed and patterned over the metal oxide layer (20). The metal oxide layer (20) is then selectively etched to form a via (24) exposing a portion of the first insulating layer (16). The first insulating layer (16) in the via (24) is then selectively etched to expose a portion of the first metal region (12). The photoresist layer (22) is removed and a second metal layer (26) is then formed over the metal oxide layer (20) and in the via (24) contacting the first metal region (12).