Stossbetrieb für Mikroprozessor mit externem Systemspeicher

A microcomputer architecture and method allows for high processing speeds. A microprocessor (106,206) constitutes the central processing unit. The microprocessor (106,206) comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit (106,206) and the...

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Bibliographische Detailangaben
Hauptverfasser: BASSETT, CAROL E., CUPERTINO, CALIFORNIA 95014, US, CAMPBELL, ROBERT G., SANTA CLARA, CALIFORNIA 95051, US, LANG, MARILYN J., MILPITAS, CALIFORNIA 95035, US, BEGUR, SRIDHAR, SAN JOSE, CALIFORNIA 95148, US
Format: Patent
Sprache:ger
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Zusammenfassung:A microcomputer architecture and method allows for high processing speeds. A microprocessor (106,206) constitutes the central processing unit. The microprocessor (106,206) comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit (106,206) and the system memory (102) communicate by way of a high speed host bus (104). The system memory (102) is comprised of multiple buses (311,312) and is capable of delivering data to the microprocessor (106,206) in a burst mode at high speeds. A memory controller (208) addresses data locations within the system memory (102) upon receipt of a first host address from the microprocessor (106,206). Accordingly, the microprocessor (106,206) can access data in the system memory (102) at an extremely fast rate when operating in a burst mode. High speed processing is accomplished without the need for an external cache.