Integrierte Schaltkreise

An integrated circuit device having an input buffer circuit is disclosed. The circuit has a single stage circuit portion for receiving a multiplexed row address (RAP_X) bit and a multiplexed column address (CAP_X) bit. Circuitry is connected to the single stage circuit portion for separately holding the received multiplexed row address bit and the received multiplexed column address bit. The single stage circuit portion may include a tri-state inverter (XTTLADD) having an tri-state control input coupled to an input buffer control signal and a latch to hold the output of the tri-state inverter (XTTLADD) when it is tri-stated by the input buffer control signal. The first circuit portion may be of the CMOS type. Such a circuit is useful in the memory support circuitry of an integrated circuit of the dynamic random access memory type.