Hochgeschwindigkeitsmultiport-FIFO-Pufferschaltung

A buffer memory for use in the output queue of a packet switching network is described. The buffer consists of two separate memories (160, 170, 260, 270) connected through a multiplexer (310) to the output of the switch. A memory access control (120, 220) processes the incoming data which arrives on...

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Hauptverfasser: DENZEL, WOLFGANG EMIL.., CH-8804 AU-WAEDENSWIL, CH, ENGBERSEN, ANTONIUS J.P..., CH-8805 RICHTERSWIL, CH
Format: Patent
Sprache:ger
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Zusammenfassung:A buffer memory for use in the output queue of a packet switching network is described. The buffer consists of two separate memories (160, 170, 260, 270) connected through a multiplexer (310) to the output of the switch. A memory access control (120, 220) processes the incoming data which arrives on only some of the input lines (130,230) and outputs it on adjacent output lines (140, 150, 240 250). The data is written concurrently into consecutive memory locations in one of the two memories (160, 170, 260, 270).