EINE FEHLERTOLERANTE DATENSPEICHERUNGSANORDNUNG

PCT No. PCT/GB90/01051 Sec. 371 Date Dec. 31, 1991 Sec. 102(e) Date Dec. 31, 1991 PCT Filed Jul. 6, 1990 PCT Pub. No. WO91/01023 PCT Pub. Date Jan. 24, 1991.A fault tolerant data storage system comprises an array of memory chips having a plurality of rows and columns, each row of memory chips CO to CN having a spare chip CS. Each chip comprises an array of memory locations some of which may be faulty. When simultaneously writing or reading data via parallel data lines DO-DN to the respective chips, a map MAP identifies any chip having a fault in the addressed location (e.g. in the addressed column) and connects the data line to a good location in the spare chip. The logical addresses for the chips are skewed differently for each other as compared with their physical addresses, such that there are not coincident faults in the different chips e.g. only a single chip in a row has a fault in the columns being simultaneously addressed in the respective chips of that row.