Verfahren zur Herstellung einer Flip-Chip-Lötstruktur für Anordnungen mit Gold-Metallisierung
A flip-chip solder bonding arrangement including a semiconductor substrate (40) having thereon layers of metallisation (42, 44, 46) which have a tendency to interact with a solder material, forming on said layers of metallisation (42, 44, 46) a barrier metallisation layer (44) which is not reactive...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | ger |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | WARNER, DAVID JOHN, NORTHAMPTON, GB PICKERING, KIM LOUISE, NORTHAMPTON NN1 3ER, GB PEDDER, DAVID JOHN, LONG COMPTON, WARWICKSHIRE, GB |
description | A flip-chip solder bonding arrangement including a semiconductor substrate (40) having thereon layers of metallisation (42, 44, 46) which have a tendency to interact with a solder material, forming on said layers of metallisation (42, 44, 46) a barrier metallisation layer (44) which is not reactive with said solder material, forming solder pads (46) on the barrier layer (44) and thereafter forming solder bonds (48) with such solder pads (46) employing said solder material. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_DE69021438TT2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>DE69021438TT2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_DE69021438TT23</originalsourceid><addsrcrecordid>eNrjZIgPSy1KS8woSs1TqCotUvBILSouSc3JKc1LV0jNzEstUnDLySzQdc4AEj6Ht5UUlxSVZpcAFaYd3lOk4JiXX5SSB1QL1J2bWaLgnp-TouubWpKYk5NZnJlaBJThYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxLq5mlgZGhibGFiEhRsZEKQIA6Po_fA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Verfahren zur Herstellung einer Flip-Chip-Lötstruktur für Anordnungen mit Gold-Metallisierung</title><source>esp@cenet</source><creator>WARNER, DAVID JOHN, NORTHAMPTON, GB ; PICKERING, KIM LOUISE, NORTHAMPTON NN1 3ER, GB ; PEDDER, DAVID JOHN, LONG COMPTON, WARWICKSHIRE, GB</creator><creatorcontrib>WARNER, DAVID JOHN, NORTHAMPTON, GB ; PICKERING, KIM LOUISE, NORTHAMPTON NN1 3ER, GB ; PEDDER, DAVID JOHN, LONG COMPTON, WARWICKSHIRE, GB</creatorcontrib><description>A flip-chip solder bonding arrangement including a semiconductor substrate (40) having thereon layers of metallisation (42, 44, 46) which have a tendency to interact with a solder material, forming on said layers of metallisation (42, 44, 46) a barrier metallisation layer (44) which is not reactive with said solder material, forming solder pads (46) on the barrier layer (44) and thereafter forming solder bonds (48) with such solder pads (46) employing said solder material.</description><edition>6</edition><language>ger</language><subject>BASIC ELECTRIC ELEMENTS ; CLADDING OR PLATING BY SOLDERING OR WELDING ; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MACHINE TOOLS ; METAL-WORKING NOT OTHERWISE PROVIDED FOR ; OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS ; OPTICS ; PERFORMING OPERATIONS ; PHYSICS ; SEMICONDUCTOR DEVICES ; SOLDERING OR UNSOLDERING ; TRANSPORTING ; WELDING ; WORKING BY LASER BEAM</subject><creationdate>1996</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19960125&DB=EPODOC&CC=DE&NR=69021438T2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19960125&DB=EPODOC&CC=DE&NR=69021438T2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WARNER, DAVID JOHN, NORTHAMPTON, GB</creatorcontrib><creatorcontrib>PICKERING, KIM LOUISE, NORTHAMPTON NN1 3ER, GB</creatorcontrib><creatorcontrib>PEDDER, DAVID JOHN, LONG COMPTON, WARWICKSHIRE, GB</creatorcontrib><title>Verfahren zur Herstellung einer Flip-Chip-Lötstruktur für Anordnungen mit Gold-Metallisierung</title><description>A flip-chip solder bonding arrangement including a semiconductor substrate (40) having thereon layers of metallisation (42, 44, 46) which have a tendency to interact with a solder material, forming on said layers of metallisation (42, 44, 46) a barrier metallisation layer (44) which is not reactive with said solder material, forming solder pads (46) on the barrier layer (44) and thereafter forming solder bonds (48) with such solder pads (46) employing said solder material.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CLADDING OR PLATING BY SOLDERING OR WELDING</subject><subject>CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MACHINE TOOLS</subject><subject>METAL-WORKING NOT OTHERWISE PROVIDED FOR</subject><subject>OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS</subject><subject>OPTICS</subject><subject>PERFORMING OPERATIONS</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SOLDERING OR UNSOLDERING</subject><subject>TRANSPORTING</subject><subject>WELDING</subject><subject>WORKING BY LASER BEAM</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1996</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIgPSy1KS8woSs1TqCotUvBILSouSc3JKc1LV0jNzEstUnDLySzQdc4AEj6Ht5UUlxSVZpcAFaYd3lOk4JiXX5SSB1QL1J2bWaLgnp-TouubWpKYk5NZnJlaBJThYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxLq5mlgZGhibGFiEhRsZEKQIA6Po_fA</recordid><startdate>19960125</startdate><enddate>19960125</enddate><creator>WARNER, DAVID JOHN, NORTHAMPTON, GB</creator><creator>PICKERING, KIM LOUISE, NORTHAMPTON NN1 3ER, GB</creator><creator>PEDDER, DAVID JOHN, LONG COMPTON, WARWICKSHIRE, GB</creator><scope>EVB</scope></search><sort><creationdate>19960125</creationdate><title>Verfahren zur Herstellung einer Flip-Chip-Lötstruktur für Anordnungen mit Gold-Metallisierung</title><author>WARNER, DAVID JOHN, NORTHAMPTON, GB ; PICKERING, KIM LOUISE, NORTHAMPTON NN1 3ER, GB ; PEDDER, DAVID JOHN, LONG COMPTON, WARWICKSHIRE, GB</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_DE69021438TT23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>ger</language><creationdate>1996</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CLADDING OR PLATING BY SOLDERING OR WELDING</topic><topic>CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MACHINE TOOLS</topic><topic>METAL-WORKING NOT OTHERWISE PROVIDED FOR</topic><topic>OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS</topic><topic>OPTICS</topic><topic>PERFORMING OPERATIONS</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SOLDERING OR UNSOLDERING</topic><topic>TRANSPORTING</topic><topic>WELDING</topic><topic>WORKING BY LASER BEAM</topic><toplevel>online_resources</toplevel><creatorcontrib>WARNER, DAVID JOHN, NORTHAMPTON, GB</creatorcontrib><creatorcontrib>PICKERING, KIM LOUISE, NORTHAMPTON NN1 3ER, GB</creatorcontrib><creatorcontrib>PEDDER, DAVID JOHN, LONG COMPTON, WARWICKSHIRE, GB</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WARNER, DAVID JOHN, NORTHAMPTON, GB</au><au>PICKERING, KIM LOUISE, NORTHAMPTON NN1 3ER, GB</au><au>PEDDER, DAVID JOHN, LONG COMPTON, WARWICKSHIRE, GB</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Verfahren zur Herstellung einer Flip-Chip-Lötstruktur für Anordnungen mit Gold-Metallisierung</title><date>1996-01-25</date><risdate>1996</risdate><abstract>A flip-chip solder bonding arrangement including a semiconductor substrate (40) having thereon layers of metallisation (42, 44, 46) which have a tendency to interact with a solder material, forming on said layers of metallisation (42, 44, 46) a barrier metallisation layer (44) which is not reactive with said solder material, forming solder pads (46) on the barrier layer (44) and thereafter forming solder bonds (48) with such solder pads (46) employing said solder material.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | ger |
recordid | cdi_epo_espacenet_DE69021438TT2 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS CLADDING OR PLATING BY SOLDERING OR WELDING CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS OPTICS PERFORMING OPERATIONS PHYSICS SEMICONDUCTOR DEVICES SOLDERING OR UNSOLDERING TRANSPORTING WELDING WORKING BY LASER BEAM |
title | Verfahren zur Herstellung einer Flip-Chip-Lötstruktur für Anordnungen mit Gold-Metallisierung |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T13%3A38%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WARNER,%20DAVID%20JOHN,%20NORTHAMPTON,%20GB&rft.date=1996-01-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EDE69021438TT2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |