Verfahren zur Herstellung einer Flip-Chip-Lötstruktur für Anordnungen mit Gold-Metallisierung

A flip-chip solder bonding arrangement including a semiconductor substrate (40) having thereon layers of metallisation (42, 44, 46) which have a tendency to interact with a solder material, forming on said layers of metallisation (42, 44, 46) a barrier metallisation layer (44) which is not reactive...

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Bibliographische Detailangaben
Hauptverfasser:	WARNER, DAVID JOHN, NORTHAMPTON, GB, PICKERING, KIM LOUISE, NORTHAMPTON NN1 3ER, GB, PEDDER, DAVID JOHN, LONG COMPTON, WARWICKSHIRE, GB
Format:	Patent
Sprache:	ger
Schlagworte:	BASIC ELECTRIC ELEMENTS CLADDING OR PLATING BY SOLDERING OR WELDING CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS OPTICS PERFORMING OPERATIONS PHYSICS SEMICONDUCTOR DEVICES SOLDERING OR UNSOLDERING TRANSPORTING WELDING WORKING BY LASER BEAM
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Beschreibung
Zusammenfassung:	A flip-chip solder bonding arrangement including a semiconductor substrate (40) having thereon layers of metallisation (42, 44, 46) which have a tendency to interact with a solder material, forming on said layers of metallisation (42, 44, 46) a barrier metallisation layer (44) which is not reactive with said solder material, forming solder pads (46) on the barrier layer (44) and thereafter forming solder bonds (48) with such solder pads (46) employing said solder material.