Integrierte Halbleiterschaltung

Described is a semiconductor integrated circuit comprising an inverter having a drive MIS transistor (Q1, Q2), a load device (R1, R2) and a transfer MIS transistor (Q3, Q4) for transferring the output of the inverter (Q1, R1; Q2, R2) to a data line (BL, BL), the channel of the drive MIS transistor being formed in the surface portion of a semiconductor substrate, and the load device being formed of a first silicon layer provided through an insulating layer on said semiconductor substrate. The channel of the transfer MIS transistor is formed of a part of a second silicon layer provided through an insulating layer on said first silicon layer, wherein one of two regions of said second silicon layer is electrically connected to the output of said inverter while the other region is connected to said data line (BL, BL). This structure may be used to provide a static memory cell of two such inverters, needing little chip area only.