Verfahren und Einrichtung für die parallele Synchronisation von mehreren seriellen Datenströmen

A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived from the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.