LAYOUT-KONSTRUKTION ZUR ADRESSIERUNG VON ELEKTROMIGRATION

A complementary metal oxide semiconductor, CMOS, device including a plurality of p-type metal oxide semiconductor, PMOS, transistors each having a PMOS drain and a plurality of n-type metal oxide semiconductor, NMOS, transistors each having an NMOS drain, comprising:at least three metal layers above the drains of the transistors, comprising a first metal layer, a second metal layer and a third metal layer; wherein the first metal layer is the lowest metal layer above the drains, the second metal layer is the next metal layer above the first metal layer and the third metal layer is the next metal layer above the second metal layer;a first interconnect on a first interconnect level on the first metal layer, connecting a first plurality of the PMOS drains together;a second interconnect on the first interconnect level connecting a second plurality of the PMOS drains together, the second plurality of the PMOS drains being different than the first plurality of the PMOS drains, the first interconnect and the second interconnect being disconnected on the first interconnect level;a third interconnect on the first interconnect level connecting a first plurality of the NMOS drains together; anda fourth interconnect on the first interconnect level connecting a second plurality of the NMOS drains together, the second plurality of the NMOS drains being different than the first plurality of the NMOS drains, the third interconnect and the fourth interconnect being disconnected on the first interconnect level,wherein the first interconnect, the second interconnect, the third interconnect, and the fourth interconnect are coupled together through at least one other interconnect level;a fifth interconnect on a second interconnect level on the second metal layer, the fifth interconnect coupling the first interconnect and the second interconnect together; anda sixth interconnect on the second interconnect level, the sixth interconnect coupling the third interconnect and the fourth interconnect together; anda seventh interconnect on a third interconnect level on the third metal layer, the seventh interconnect coupling the fifth interconnect and the sixth interconnect together; and preferably wherein an output of the device is connected to the seventh interconnect. A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The