Speicherzugriffsverzögerungs-Steuerkreis für Bildwanderungsausgleich

A memory access delay control circuit for image motion compensation in HDTV, which can adaptively delay read/write time of two frame memories and simply control the delay amount data. The circuit includes a section for providing delay amount data of a write address signal of the frame memories, a delay control section for providing delay control signal for delaying the write address signal as much as the value of the delay amount data, and an address counter section for counting and providing the write address signal in accordance with the delay control signal. According to the present invention, the delay amount data providing section may comprise a section for detecting actual delay amount of the write address signal by utilizing a frame synchronizing signal and a frame synchronizing write signal so as to automatically compensate for the inputted delay amount, thereby providing convenience in use.