Circuit arrangement for switching PCM channels

The invention relates to a circuit arrangement for switching PCM channels in base band, the serial data to be switched and arriving an n input ports being parallel-converted block by block, temporarily stored in a memory and, after read-out, again being supplied serialised to n output ports which are in each case allocated to one or more destination addresses, and is characterised by the fact that a first temporary storage of the parallel-converter data blocks occurs in n input registers R allocated to the n input ports, that then a second temporary storage occurs in a RAM memory in such a manner that the data blocks are written in successively in accordance with their input order under a memory address which is sequentially incremented (incrementing), and that the data blocks are read out as determined by the number of the output port or the time slot contained in the destination address or allocated to the destination address and are again temporarily stored in an output register R which are in each case allocated to the n output ports (Figure 1).