Circuit arrangement for memory access in a multi-processor system

A multi-processor system contains several processor units (for example microcomputers), the buses of which are connected to one another and between which data are exchanged if necessary. To keep down the complexity for the access of a processor unit to the memory of another processor unit, the buses (BSA, BSB) of the individual processor units (REA, REB) are coupled via an interface and control circuit (BIS). The individual processor is associated with an evaluating circuit by means of which the output signals of the processor units (REB) are evaluated and from this a selection signal (EXMEM) is generated by means of which the access to the memory (SPA) of another processor unit (REB) is enabled via the control circuit (BIS) of the individual processor unit (REB).