Circuit arrangement for PLL speed control, with automatic setting of the operating point

The invention relates to a circuit arrangement for PLL speed control, with automatic setting of the operating point, especially for electronically commutated motors in cassette drive mechanisms. The object of the invention is to find a circuit arrangement for PLL speed control in which the optimum operating point for the phase-difference signal is set automatically when running on no-load or basic load. This is achieved according to the invention in that the actual speed value is formed from the sum of the rectified generator voltage and a voltage which is proportional to phase difference, the static speed deviation in the locked state of the phase control loop is, furthermore, zero, and hence the e.m.f. supplied by a generator coupled to the motor, or the motor e.m.f. itself, is used as a reference voltage, making use of an analog memory.