Circuit arrangement for monitoring electronic computer chips

A circuit arrangement for monitoring electronic computer chips is proposed which output periodic signals at one of their outputs when operating correctly. Two series-connected retriggerable timing sections (11, 14) trigger a signal generator stage (15) which is preferably constructed as a timing section and which generates a reset signal for the computer chip (10). The periodic signals trigger the first timing section (11) which sets a minimum permissible signal spacing whilst the second timing section (14) sets a maximum permissible signal spacing. To be able to generate a sequence of reset signals even when the signal sequence (U10) is too fast, these are additionally supplied to the trigger input of the second timing section (14).