Circuit arrangement for storing data groups arranged in tabular form

The circuit arrangement, which can be used, for example, for buffer storage of telephone numbers for call barring purposes in PBX systems, has a random-access memory and a memory controller by means of which the memory spaces intended for data input or output are activated. To design the memory access in flexible fashion, the memory contains a plurality of semiconductor chips (RAM 0,..., RAM 3) disposed in parallel, in which the individual data elements (e.g. telephone number digits) arriving in serial fashion are stored in parallel, and the memory controller contains a decoder (DEC) which, on the basis of a first input signal (ZN) which identifies the respective memory chip and of a second input signal (CEW) which defines the input time, generates an output signal (E0, ..., E3) which is fed to the release input (EN) of the memory chip which is to be activated.