MOS read-write memory with spare cells for malfunction handling - has spare cells accessed by inbuilt ROM stages and has read differential amplifier in each column

An MOS read-write memory is designed with additional cells to cater for malfunctions. The auxiliary cells are identified by addresses held in a read only memory stage. The memory matrix of the circuit (10) is based upon 256 lines and 256 columns and is split into two sections (10a,10b). In the centre of the matrix are 256 read amplifiers (11) Line and column decoders (12,19) are built into the unit. Erasable programmable read only memories (36) are built into each half matrix to identify and access the auxiliary cells.