Control programme test unit for microprocessor - has comparator stage to check validity of selected locations in erasable PROM

A microprocessor system operates together with a programme test facility based upon stops located within an erasable programmable read only memory (EPROM). A microprocessor control unit (1') is coupled over an address bus (3), data bus (5) and control bus (4) with an EPROM (6) holding the control programme and test unit (9). An interrupt unit (7) handles requests from external devices (8). The test unit receives the addresses and stores a value in a register when a decoder identifies a stop instruction continued in the control programme. Whe a stop does occur the register state is compared with the value stored and a proceed instruction is initiated. If the comparison is not satisfactory, an error is indicated.