DE2846331

A functional and structural arrangement for charge-coupled device binary or multi-level storage systems of a modified serial-parallel serial type memory block arrangement wherein the output sequence is removed from the memory block proximate to the location where the original sequence was entered into the memory block. The structure includes two memory block portions designated as the left and right memory block portions. The input information sequence is entered into the upper left side of the right memory block portion in serial fashion, is moved in parallel to the bottom of the right memory block portion and serially removed from the lower left side of the right memory block portion and entered into the lower right side of the left memory block portion. The sequence is moved in parallel to the top of the left memory block portion and serially removed from the upper right side of the left memory block portion proximate to the original input location for comparison to the reference charge sequence in an analog-to-digital regeneration operation utilizing the same digital-to-analog converter.