Logic analyser with one or more channels - has main and auxiliary data shift registers and trigger units to assemble data strings

The logic analyser includes a number of parallel channels, typically three. Each channel comprises a data shift register and an auxiliary shift register. The output stages of the auxiliary shift register transfer data to trigger units. The trigger units provide bit sequences which each fill up the next available cell of an operational circuit. The latter is also connected to a computer terminal and a pulse generator. The multiple channel arrangement enables a number of bit lengths of various types to be assembled.