DE2818675

At a subscriber station AU communicating with a central office of a data network, a logic unit UM includes a processing subunit UE which, under the control of a microprogrammed subunit UC comprising a microinstruction memory MM and a sequencer SQ, digitally demodulates an incoming carrier and synthesizes an outgoing carrier modulated in the DPSK (differential-phase-shift keying) mode. The modulation is effected by multiplying stored bits of an outgoing signal, read out from a data memory MD, with bits representing digitized sine and cosine samples of the carrier wave obtained from a calculator AL within subunit UE, followed by conversion to analog form and filtering; demodulation is carried out in a similar manner, after conversion of analog samples of the incoming carrier to digital form, by multiplying the resulting bits with those of the calculated sine and cosine samples. The sampling instants are established by a timing signal T2 digitally synchronized with the central-office clock through a phase-locking loop including an adjustable frequency divider DP controlled by an error signal from the calculator AL, emitted when the peak-indicating derivative sample has an absolute value exceeding a predetermined threshold.