MOS address buffer selector circuit - has two-condition trigger stage and switching network permitting dynamic operation

The MOS address buffer selector circuit has a control stage between the controlled stage of a driver transistor and a reference voltage source. This control stage consists of the channel of a scanning transistor and the channel of an information transistor selectable via an address input. A switching circuit loads the controlled stage of the driver transistors with the reference voltage after the address data has been received into the two-condition trigger stage.