SCHALTUNGSANORDNUNG ZUM WIEDERGEWINNEN VON DATENSIGNALEN AUS EINER FOLGE VON DATEN- UND TAKTSIGNALEN

Data and clock bits are sampled by use of two delay means such as shift registers which are enabled at a clock rate which is set so that a first such delay means coupled to receive the bits includes no more than one bit therein at any time. The receipt of a bit substantially at the midway point of t...

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Bibliographische Detailangaben
1. Verfasser:	J. RATHBUN,DONALD
Format:	Patent
Sprache:	ger
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY INFORMATION STORAGE INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	Data and clock bits are sampled by use of two delay means such as shift registers which are enabled at a clock rate which is set so that a first such delay means coupled to receive the bits includes no more than one bit therein at any time. The receipt of a bit substantially at the midway point of the second delay means, which is coupled serially to receive bits from the first delay means, causes a sampling signal to be generated in response to which a determination is made as to whether another bit has been received by the first delay means. Further logic is provided to recover the data bits.