DE2705190

A signal detector monitoring the presence or absence of line currents in a multiplicity of circuits of a telecommunication system includes an orthogonal matrix MN of magnetic-core sensors divided into (m+1) rows and (n+1) columns. The cores of the first m rows and first n columns constitute active s...

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1. Verfasser: MICHELI, SPIRIDIONE DE, TURIN (ITALIEN)
Format: Patent
Sprache:eng
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Zusammenfassung:A signal detector monitoring the presence or absence of line currents in a multiplicity of circuits of a telecommunication system includes an orthogonal matrix MN of magnetic-core sensors divided into (m+1) rows and (n+1) columns. The cores of the first m rows and first n columns constitute active sensors provided with respective writing conductors extending from mxn monitored circuits. A duplicated first set of wires 1A, 1B, each coacting with the cores of one row, are successively energized with interrogation and resetting currents in the course of a scanning cycle; a duplicated second set of wires 2A, 2B, each coacting with the cores of one column, terminate at respective sense amplifiers AS which read the states of the interrogated cores and load the detected responses into a buffer register RPP from which they are serially read out to a processor DU. The duplicated first wires 1A, 1B are energized in alternate cycles by respective scanners IR in two control sections CMA, CMB which also include the corresponding sense amplifiers AS; each control section further comprises a checking network CC including two test units CAS, CIR respectively designed to ascertain possible malfunctions of the associated sense amplifiers AS and of the associated scanner IR. Test unit CAS is enabled at the end of each scanning cycle to receive the output signals of the amplifiers appearing upon the interrogation and the subsequent resetting of the cores of the (m+1)th row whereas unit CIR is enabled during flow of interrogation current in each row-scanning interval to receive the output signal of the last amplifier AS(n+1) representing the response of the (n+1)th core of each row, all these cores constituting passive sensors devoid of writing conductors. The results of the checks carried out by the test units are fed to the processor during the time interval allocated to the scanning of the (m+1)th row.