DE2633558

A storage module has storage cells which are arranged between word lines and bit lines and which contain a storage capacitor and a cell selector transistor. Each bit line is divided into two bit line portions with a read-out amplifier connected to each bit line portion. In each bit line portion there is arranged a compensation cell which contains a selector transistor connected to the bit line portion and a capacitor is connected between an operating voltage and the selector transistor. Prior to a read-out process, the connection point between the capacitor and the selector transistor of the compensation cell is charged to a different operating voltage such that, at the beginning of the read-out process, the bit portion is set to a middle voltage located in the middle between the potential assigned to a binary "1" and the potential assigned to a binary "0". The capacitance of the selector transistor and the capacitor of the compensation cell are selected to be such that the increase in capacitance which occurs on the bit line portion as a result of the selection of the selector transistor and which is produced by the sum of the capacitances of the capacitor and of the selector transistor is equal to the increase in capacitance which occurs on the other bit line portion as a result of the selection of a storage cell.