SCHALTUNGSANORDNUNG ZUM VERSETZEN DER DATENKOEPFE EINES PLATTENSPEICHERS UM EINEN DEFINIERTEN BETRAG AUS DER DATENZYLINDERMITTE

A circuit arrangement offsets the data heads of a data cylinder memory by a determinate amount from the mid-position of the data cylinder and uses a fine regulating circuit and a coarse regulating circuit. The circuit arrangement includes a track difference register, a digital/analog converter connected to the track difference register, and arrangement for forming the sign and a function generator, in which the amount of the desired track offset is input, in digital form, into the track difference register, and which is converted into an analog value by the subsequently connected digital/analog converter. The sign of the offset is produced in the coarse regulating circuit which has an arrangement provided for normal positioning. An analog switch is connected between the input and output of the function generator and linearizes the function generator when the same is closed when the regulating circuit is transferred to fine regulation. The output of the function generator is connected to a summing point located in the fine regulating circuit and at which the position error signal is supplied.