DYNAMISCHE SPEICHEREINRICHTUNG

1456326 Transistor stores WESTERN ELECTRIC CO Inc 8 July 1974 [11 July 1973] 30121/74 Heading H3T A memory cell includes a read transistor 60 having its controlled path connected between storage means 70 and a read data line 21, a write transistor 50 having its controlled path connected between a write data line 22 and the storage means 70, and a single select line 10 connected in common to the control electrodes of both transistors 50 and 60, said write transistor 50 having a greater threshold voltage than the read transistor 60 to improve discrimination between read and write signals. In the " off " state a high level V OFF signal is applied to line 10 to turn off both transistors 50 and 60 so that data line 20 is at an indeterminate state. To write, a write data signal V R is applied on line 20 and a signal V W #V SS -V T60 -V T50 is applied on line 10, where V SS is the voltage on line 30, V T60 is the threshold voltage of transistor 60, V T50 is the threshold voltage of transistor 50. These two signals turn on transistors 50, 60 and the data is applied to node 75. To read out the stored data, a read data signal is applied to line 10 turning on transistor 60, and the line 20 is precharged to a logical " 1 " state. If a " 0 " is stored, the level at node 75 holds transistor 70 off, and the line 20 remains at the " 1 " level. If a " 1 " is stored, this turns transistor 70 on, and the line 20 discharges through transistors 60, 70 to a " 0 " level. Readout is thus in an inverted form, and an inverter may be connected to line 21 to return it to the correct sense. In order to prevent transistor 50 from becoming conductive during readout the voltage on line 10 must be precisely controlled.