Semiconductor arrangement for memory-store elements - has two adjacent zones bedded in main material zone of opposed conductivity

The semiconductor arrangement for memory store elements is designed to combine the advantages of both static and dynamic techniques and to compensate for the discharge of storage capacities through leaks. The arrangement comprises a plate-type semiconductor crystal of one conductive type, in which two adjacent zones of opposed conductivity are generated by masked diffusion. Their pn-junctions with the remainder of the material are covered by an insulating layer. Each of the zones has its own electrode contact with a controlling voltage source being arranged between one of the zone electrodes and the material electrode. A working impedance is incorporated between the latter electrode and the other zone electrode.