SCHADHAFTE SPEICHERZELLEN ENTHALTENDES MONOLITHISCHES HALBLEITERCHIP GERINGER VERLUSTLEISTUNG

A memory array chip constructed from field effect transistors (FET) which is particularly suitable for use in systems wherein only a portion of the total memory capacity of a chip is used. The chip contains two or more separate memory arrays, each substantially isolated from the others. If one of th...

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1. Verfasser: KEMERER, DOUGLAS WAYNE, ESSEX JUNCTION, VT. (V.ST.A.)
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creator KEMERER, DOUGLAS WAYNE, ESSEX JUNCTION, VT. (V.ST.A.)
description A memory array chip constructed from field effect transistors (FET) which is particularly suitable for use in systems wherein only a portion of the total memory capacity of a chip is used. The chip contains two or more separate memory arrays, each substantially isolated from the others. If one of the arrays is not to be utilized, power may be removed therefrom.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_DE2332555A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>DE2332555A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_DE2332555A13</originalsourceid><addsrcrecordid>eNqNikEKwjAUBbtxIeodcgEXNuQAMXntD8S0JL8uClKKxJVood4fs_AAbt7wmNlWt2RIW9INQ6QezhDiCO8RBAKT9oxgkcSlC513TK705RZx9nCMaMj1okV0oYy4IvohcVGJh9Duq81jfq758OOuEg3Y0DEv7ymvy3zPr_yZLGopa6WUPsk_ki_y9DMJ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SCHADHAFTE SPEICHERZELLEN ENTHALTENDES MONOLITHISCHES HALBLEITERCHIP GERINGER VERLUSTLEISTUNG</title><source>esp@cenet</source><creator>KEMERER, DOUGLAS WAYNE, ESSEX JUNCTION, VT. (V.ST.A.)</creator><creatorcontrib>KEMERER, DOUGLAS WAYNE, ESSEX JUNCTION, VT. (V.ST.A.)</creatorcontrib><description>A memory array chip constructed from field effect transistors (FET) which is particularly suitable for use in systems wherein only a portion of the total memory capacity of a chip is used. The chip contains two or more separate memory arrays, each substantially isolated from the others. If one of the arrays is not to be utilized, power may be removed therefrom.</description><language>ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>1974</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19740117&amp;DB=EPODOC&amp;CC=DE&amp;NR=2332555A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19740117&amp;DB=EPODOC&amp;CC=DE&amp;NR=2332555A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KEMERER, DOUGLAS WAYNE, ESSEX JUNCTION, VT. (V.ST.A.)</creatorcontrib><title>SCHADHAFTE SPEICHERZELLEN ENTHALTENDES MONOLITHISCHES HALBLEITERCHIP GERINGER VERLUSTLEISTUNG</title><description>A memory array chip constructed from field effect transistors (FET) which is particularly suitable for use in systems wherein only a portion of the total memory capacity of a chip is used. The chip contains two or more separate memory arrays, each substantially isolated from the others. If one of the arrays is not to be utilized, power may be removed therefrom.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1974</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNikEKwjAUBbtxIeodcgEXNuQAMXntD8S0JL8uClKKxJVood4fs_AAbt7wmNlWt2RIW9INQ6QezhDiCO8RBAKT9oxgkcSlC513TK705RZx9nCMaMj1okV0oYy4IvohcVGJh9Duq81jfq758OOuEg3Y0DEv7ymvy3zPr_yZLGopa6WUPsk_ki_y9DMJ</recordid><startdate>19740117</startdate><enddate>19740117</enddate><creator>KEMERER, DOUGLAS WAYNE, ESSEX JUNCTION, VT. (V.ST.A.)</creator><scope>EVB</scope></search><sort><creationdate>19740117</creationdate><title>SCHADHAFTE SPEICHERZELLEN ENTHALTENDES MONOLITHISCHES HALBLEITERCHIP GERINGER VERLUSTLEISTUNG</title><author>KEMERER, DOUGLAS WAYNE, ESSEX JUNCTION, VT. (V.ST.A.)</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_DE2332555A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>ger</language><creationdate>1974</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>KEMERER, DOUGLAS WAYNE, ESSEX JUNCTION, VT. (V.ST.A.)</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KEMERER, DOUGLAS WAYNE, ESSEX JUNCTION, VT. (V.ST.A.)</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SCHADHAFTE SPEICHERZELLEN ENTHALTENDES MONOLITHISCHES HALBLEITERCHIP GERINGER VERLUSTLEISTUNG</title><date>1974-01-17</date><risdate>1974</risdate><abstract>A memory array chip constructed from field effect transistors (FET) which is particularly suitable for use in systems wherein only a portion of the total memory capacity of a chip is used. The chip contains two or more separate memory arrays, each substantially isolated from the others. If one of the arrays is not to be utilized, power may be removed therefrom.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
title SCHADHAFTE SPEICHERZELLEN ENTHALTENDES MONOLITHISCHES HALBLEITERCHIP GERINGER VERLUSTLEISTUNG
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T16%3A39%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KEMERER,%20DOUGLAS%20WAYNE,%20ESSEX%20JUNCTION,%20VT.%20(V.ST.A.)&rft.date=1974-01-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EDE2332555A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true