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1393645 Automatic exchange systems INTERNATIONAL STANDARD ELECTRIC CORP 5 April 1973 [11 April 1972] 16272/73 Heading H4K In a switching network having a number of parallel sub-networks, the control system attempts to select two paths for each call to be set up through the network, one in each of two different sub-networks, and means are provided for establishing only one of two chosen paths whilst the second is kept in reserve in case of a break, e.g. due to a fault in the corresponding sub-network, in the active path. Where only one path is available that path is established, and where a path is being held in reserve, one of the two paths is dropped if any part of one of them is required for a further call. The embodiments relate to time-space-time networks in a T.D.M. system, the network of Fig. 1 (not shown), being divided only in the space division stage into two sub-networks and the network shown in Fig. 2, being divided throughout into two basic sub-networks. Referring to Fig. 2, 32 input T.D.M. stages 1a are associated with a space division sub-network 5 and 32 input T.D.M. stages with space division sub-network 6. 64 Groups of 8, 32 channel T.D.M. highways, serving 16,000 subscribers are attached to the network, each highway being connectable with two input T.D.M. stages, one in each sub-network. A similar arrangement exists at the output side of the network. In each T.D.M. input stage such as 1a. the channels on 8 highways are supermultiplexed at 12a for feeding, to a 256 position store 10a. 8 Bit speech samples are transferred in parallel via buffer 11a and space division sub-network 5 to an output T.D.M. stage, each space division sub-network having 32 inputs and 32 outputs and comprising three stages. Both space division networks 5, 6 are non-blocking and the network as a whole is non-blocking for setting up one path per call. In operation, under control of computer 3 and clock 4 an attempt is made to reserve a path through each sub-network for each call. If successful, the speech samples are fed through both paths from the input T.D.M. stages, e.g. 1a, 1b, through the respective space division networks to the output stages, validation bits stored in speech store address memories 27a, 27b, govern- ing which of the two speech samples is fed to a respective 256 position output store 28a, 28b, thereby ensuring only one of the two identical speech samples is fed to an outgoing highway. In the Fig. 1 (not shown) embodiment, all 64 T.D.M. input stag