MULTIPLEXIERSYSTEM FUER ADRESSENDEKODIERLOGIK

Address decode logic is multiplexed for selectively decoding input address of a read-only memory (ROM) and a random-access memory (RAM) and for supplying the decoded addresses to the appropriate one of the memories. ROM and RAM input signal paths are controlled in alternate succession to alternately apply ROM and RAM address input signals to the decode logic. Output signal paths from the decode logic to both the ROM and the RAM are similarly controlled in alternate succession to supply decoded address signals to the appropriate one of the memories. The arrangement is implemented using field effect transistors.