DE2226382

1387043 Data processing INTERNATIONAL BUSINESS MACHINES CORP 24 May 1972 [10 Sept 1971] 24344/72 Headings G4A and G4C A digital data processing system comprises a main memory 9 and processors 1, each processor having its own buffer memory 2 and control unit 6 through which it is connected to the memory. Each control unit 3 is connected to all the other control units, responds to requests from its processor 1 for data not available in the buffer store and transmits such requests to each of the other control units. These are responsive to the requests to determine if a modified version of the requested data is held in their associated buffer and, if so, to transmit the modified data to the requesting processor. The buffer memories 2 have a higher access speeds than memory 9, and include a cache which stores data and one (or more) directories for address data and validity bits. There is twoway set associative mapping between the buffer and the main memory and the processor may operate on pipelined instructions. Requests for access to the main memory pass to the control unit 6 (Fig. 4, not shown) and a memory busy directory is checked to ensure that the memory area is free. Then a request is selected according to a priority system and transmitted to all the other control units. The requests from the various control units are again examined on a priority basis and one is chosen. The originating control unit then transmits to main storage the selected request to start the memory cycle and, simultaneously, each control unit sends the request to its buffer store. If modified data relating to the requested data is there, it is immediately returned to its control unit which modifies the data in main memory 3. It is also passed to the requesting processor. By this procedure modified data is thus fetched through main memory from a buffer memory without requiring an additional storage cycle.