EINRICHTUNG UND VERFAHREN ZUM BETRIEB DER EINRICHTUNG ZUR FEHLERPRUEFUNG UND FEHLERLOKALISIERUNG IN EINEM MODULAREN DATENVERARBEITUNGSSYSTEM

In a modular data processing system wherein the individual processing units are linked with each other via a bus system and with a central control, a tester is provided in each processing unit. The tester includes a test reply information register, an address generator for generating the processing unit address, a compare circuit for comparing the address transferred from the control unit via the address bus and stored in the address register with the processing unit address, a pattern generator for terminating the address bus with a given bit pattern of correct parity, a parity check circuit for signalling parity errors on the address bus, and a parity circuit for generating the correct parity bit from the bit pattern on the data bus. The output bits of these parity circuits together with the generated processing unit address are fed to the test reply information register for transmission. The tester also includes a control circuit for controlling the transmission of the addresses, the data patterns, and the test reply information.