DE2015712

1305771 Digital data processors WESTERN ELECTRIC CO Inc 2 April 1970 [3 April 1969 21 Oct 1969] 15603/70 Heading G4A [Also in Division H4] A register sender system comprises a common store having a plurality storage locations which receive signal information for different destinations, a corresponding plurality of sending devices each arranged to transmit the associated signal information in serial form and to modify the association stored information in accordance with each signal element transmitted, and an independently operating control unit which monitors the stored signal informations and enables and disables each sending device in accordance with its stored information. As described a telephone exchange employs two processors sharing a common memory and common peripheral access circuitry. One processor is a wired programme processor which is capable of performing various routine tasks such as detecting individual dial pulses of a digit and adding each detected pulse to a stored total, while the other is a programme controlled processor which performs the main tasks associated with the control of the exchange and which supervises the operations of the wired logic processor, e.g. to detect interdigit pauses &c., and to set up that processor to receive a further digit or to perform another of its routine tasks. The routine tasks performed by the wired processor are reading from store data words and entering them in a data sender, servicing digit receivers and senders and associated originating registers during the reception or transmission of the pulses of a digit, and scanning subscriber lines and trunks for calling condition. These tasks although relatively simple require frequent actions at intervals determined by external conditions (e.g. by data sending and pulse rate employed) and thus the inclusion of a wired processor avoids the frequent interrupts in the stored programme processor that would otherwise be necessary. The stored programme processor normally has priority in the use of the common memory and common peripheral access circuitry. The wired processor must (a) complete the serving of the data sender before the end of each 1À251 millisecond cycle and (b) service a group of digit receivers and senders before or immediately after the end of a cycle (different groups being serviced in successive cycles). If 24 microseconds before the end of a cycle (a) is not completed due to being unable to gain access to the common memory a flp-flop is at