Detektorvorrichtung zum Erfassen abnormaler Takte

Frequencies of clocks CLK1 and CLK2 are divided in frequency divider circuits (11 to 14), frequency-divided clocks CLK1A and CLK1B are input into clock comparators (15) and (16). Frequency-divided clocks CLK2A and CLK2B are input into clock comparators (15) and (16). The clock comparator (15) counts...

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Bibliographische Detailangaben
1. Verfasser:	TSUZUKI, TAKAYUKI
Format:	Patent
Sprache:	ger
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PULSE TECHNIQUE TESTING
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Beschreibung
Zusammenfassung:	Frequencies of clocks CLK1 and CLK2 are divided in frequency divider circuits (11 to 14), frequency-divided clocks CLK1A and CLK1B are input into clock comparators (15) and (16). Frequency-divided clocks CLK2A and CLK2B are input into clock comparators (15) and (16). The clock comparator (15) counts the number of pulses of the clock CLK1A based on the clock CLK2B and outputs an error signal ERR1. The clock comparator (16) counts the number of pulses of the clock CLK2B based on the clock CLK1B and outputs an error signal ERR2. An abnormal clock is detected by examining states of the error signals ERR1 and ERR2.