Digital-zu-Analog-Wandler-Vorrichtung und Verfahren zum Verbessern der integralen Nichtlinearitätsanpassung derselben

An apparatus and method, which improves both the matching of the integral non-linearity of multiple resistor-string based DACs connected in parallel between two different reference voltages and the charge/discharge time of the parasitic capacitances associated with middle nodes of the DAC resistor strings, is presented. In a device where a plurality of DACs are connected in parallel between a first reference voltage and a second reference voltage, and each DAC is implemented using a plurality of resistors coupled in series between the two reference voltages, the resistor string in each DAC is partitioned into a plurality of subsets. A DAC node is located between each subset in each DAC, such that each DAC includes corresponding resistor subsets and corresponding DAC nodes. Each set of corresponding DAC nodes are respectively coupled to a different proportional reference voltage, which is maintained at a voltage level equal to the steady-state voltage potential across its respective corresponding DAC nodes and the first reference voltage. The different proportional reference voltages are implemented using either separate ideal voltage sources, or a master resistor string. The master resistor string, which comprises a plurality of series-connected resistors, is coupled between the first and second reference voltages. The master resistor string includes a corresponding master node for each of the different proportional reference voltages required, which provides a lower impedance path between the respective node and the two reference voltages.