Flat semiconductor module with several semiconductor units in parallel

Each semiconductor unit consists of two main surfaces and two sets of main and gate electrodes (13), one of which is located on one main surface. The level of the gate electrode and gate electrode coupling gate line is lower than the level of the main electrode. One gate electrode line of each unit...

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Hauptverfasser: KODAMA, HIRONORI, HITACHI, IBARAKI, JP, NAGASU, MASAHIRO, HITACHINAKA, IBARAKI, JP, KOHNO, YASUHIKO, HITACHI, IBARAKI, JP
Format: Patent
Sprache:eng ; ger
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Zusammenfassung:Each semiconductor unit consists of two main surfaces and two sets of main and gate electrodes (13), one of which is located on one main surface. The level of the gate electrode and gate electrode coupling gate line is lower than the level of the main electrode. One gate electrode line of each unit extends over the latter. The ratio of the width and interval of the gate electrode line is at least 1:2.