Bundle forming channel for ultrasound image sender

The channel includes an A-D converter (54) which outputs digital sampled values. A delay circuit (56) carries out delays by integer sample periods and has an input for the digital samples. A further delay circuit (58) carries out delays by a fraction of sample periods and has an input for the digita...

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Bibliographische Detailangaben
Hauptverfasser:	LILLEGARD, GREGORY A., GREENFIELD, WIS., US, MILLER, STEVEN C., WAUKESHA, WIS., US, MILON, DANIEL C., MILWAUKEE, WIS., US
Format:	Patent
Sprache:	eng ; ger
Schlagworte:	ACOUSTICS ACOUSTICS NOT OTHERWISE PROVIDED FOR ANALOGOUS ARRANGEMENTS USING OTHER WAVES DEAF-AID SETS DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES DIAGNOSIS ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY HUMAN NECESSITIES HYGIENE IDENTIFICATION INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION ORRERADIATION OF RADIO WAVES LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKEACOUSTIC ELECTROMECHANICAL TRANSDUCERS MEASURING MEDICAL OR VETERINARY SCIENCE METHODS OR DEVICES FOR PROTECTING AGAINST, OR FOR DAMPING,NOISE OR OTHER ACOUSTIC WAVES IN GENERAL MUSICAL INSTRUMENTS PHYSICS PUBLIC ADDRESS SYSTEMS RADIO DIRECTION-FINDING RADIO NAVIGATION SOUND-PRODUCING DEVICES SURGERY TESTING
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Beschreibung
Zusammenfassung:	The channel includes an A-D converter (54) which outputs digital sampled values. A delay circuit (56) carries out delays by integer sample periods and has an input for the digital samples. A further delay circuit (58) carries out delays by a fraction of sample periods and has an input for the digital samples of the first delay circuit. A delay control circuit (106) is connected with both delay circuits and outputs delay signals which control dynamically and synchronously the amount for delaying the signals going through the delay circuits. The first delay circuit includes a FIFO register (101) with an input for the digital samples. A first register (102) with an output for the input coupled to the FIFO register. The second delay circuit includes an interpolator (107) with a first input (IN) which is coupled to the output of the first register.