Panikfallen-System und -Verfahren

A panic trap system recovers from inaccurate results produced from out of order execution of instructions in a processor. The panic trap system includes a fetch mechanism (IFETCH) that fetches instructions from an instruction cache. Two queues receive the instructions from the fetch mechanism and execute the instructions out of order. Specifically, an ALU instruction queue (AQUEUE) receives instructions that are directed to the ALU. A memory instruction queue (MQUEUE) receives instructions that are directed to a data cache (DCACHE) or a main memory. The MQUEUE includes instruction registers and corresponding address reorder buffer slots (ARBSLOTs) for receiving memory instructions and data addresses corresponding to the results of instruction execution, respectively. Trap indicator logic is associated with each ARBSLOT for recognizing an architecturally incorrect execution of a memory instruction and for associating a nonarchitectural panic trap indicator with the instruction after execution. After an instruction is executed in either the AQUEUE or the MQUEUE, it is retired by the retire mechanism. During the retirement process, upon recognizing the panic trap indicator, a trap vector generator associated with the retire mechanism purges instructions from the AQUEUE and the MQUEUE and causes the IFETCH to recommence fetching, beginning with a new instruction address to remedy the panic trap event. Additionally, the panic trap system can be used by the IFETCH and the system interface control for timing and synchronization reasons, and it can be used by the DCACHE to recover from parity errors.