Halbleiterspeichereinrichtung und Verfahren zum Auswählen einer Wortleitung in einer Halbleiterspeichereinrichtung

A disturb mode control circuit designates a disturb mode for activating an internal cycle setting circuit in response to a predetermined state of an address signal at a terminal when a disturb mode designating signal applied from a control circuit is active. The activated internal cycle setting circ...

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1. Verfasser: NAGASE, KOUICHI
Format: Patent
Sprache:ger
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Zusammenfassung:A disturb mode control circuit designates a disturb mode for activating an internal cycle setting circuit in response to a predetermined state of an address signal at a terminal when a disturb mode designating signal applied from a control circuit is active. The activated internal cycle setting circuit continuously issues a clock signal having a predetermined period to the control circuit. In accordance with the mode detection signal applied from the disturb mode control circuit and the clock signal applied from the internal cycle setting circuit, the control circuit successively generates an internal address signal in synchronization with the clock signal applied from an internal address generating circuit for selecting the word line in a memory cell array.