Elektrisch programmierbare Speicherzellenanordnung und Verfahren zu deren Herstellung

An electrically programmable memory cell array has parallel rows of individual memory cells located alternately between and at the bottom of longitudinal trenches (5) extending parallel to the rows in a semiconductor substrate (1), insulation structures (3, 8) being provided for insulating adjacent...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	HOFMANN, FRANZ. DR., 80995 MUENCHEN, DE, KRAUTSCHNEIDER, WOLFGANG. DR., 83104 TUNTENHAUSEN, DE, RISCH, LOTHAR. DR., 85579 NEUBIBERG, DE, REISINGER, HANS. DR., 82031 GRUENWALD, DE
Format:	Patent
Sprache:	ger
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	An electrically programmable memory cell array has parallel rows of individual memory cells located alternately between and at the bottom of longitudinal trenches (5) extending parallel to the rows in a semiconductor substrate (1), insulation structures (3, 8) being provided for insulating adjacent rows from one another. Each memory cell comprises at least one MOST, having a gate dielectric (7) of material with traps. Word lines (9) extend transversely to the rows, each being connected to the gate electrodes of MOST of different rows. Also claimed is a process for production of the array.