Integrierte Schaltmatrix mit Feldeffekttransistoren

1,150,336. Decimal half-adders. INTERNATIONAL BUSINESS MACHINES CORP. 17 Jan., 1967 [17 Jan., 1966], No. 2358/67. Heading G4A. [Also in Division H1] A switching matrix is formed by an array of field-effect transistors arranged in rows and columns on a common semi-conductor substrate. The transistors in each row have a common source electrode and those in each column have a common gate electrode. Means are provided for selectively applying drive pulses to the common source electrodes as are means for selectively applying gating pulses to the common gate electrodes. The embodiments describe the use of IGFETs operating in the enhancement mode, but it is stated that unipolar transistors may be used. In the construction of Fig. 1 the source diffusions S0-S9, S10-S19 and drain diffusions D are made simultaneously by diffusion of phosphorus into a high resistivity silicon wafer through holes in a genetic silica coating which regrows during the process. The gate electrodes G0-G9, G10-G19 are formed by completely coating the insulated wafer with aluminium which is then selectively removed. The matrix consists of transistors T00-T99. The wafer additionally contains driver transistors DR0-DR9 whose drain electrodes are respectively formed by the extended source diffusions S0-S9 of the matrix. The load R associated with a particular transistor is energized along when the appropriate driver transistor DR and gate G are activated by conventional pulse sources PS2, PS1. In the similar decimal half-adder of Fig. 4 the source and drain electrodes of the matrix and its driving transistors are made by a first diffusion process. The " horizontal " crossunder connectors 0-9 and 0-18 may be formed by a surface metallization pattern over the insulating oxide or may be formed by a second diffusion process yielding N+ patterns in the surface of the wafer. In the latter case the linking " vertical " cross-unders are then made by surface metallization at the same time as the formation of the gate electrodes G0-G9, G10-G19 of the matrix and driving transistors. In operation a decimal digit is fed in from source DS 1 simultaneously with a second digit from the other source DS2, and the cross-under 0-18 corresponding to the sum of the digits is energized.