DE1549474

1,156,249. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 21 Sept., 1967 [28 Sept., 1966], No. 43028/67. Heading G4A. In a data processing system, devices connected to a bus hold tags to control distribution of data on the bus between the devices, or provision is made for transferring the tag of one device to another device. In a floating point processing unit (Fig. 17A) of the system, main storage feeds floating point buffers FLB and is fed from store data buffers 244 (each of which has an associated tag register). Three reservation units RU1, RU2, RU3 (only one shown explicitly), each capable of registering two operands and a tag associated with each operand, can feed an adder (with provision for subtraction) unit 188. A similar two reservation units RU4, RU5 can feed a multiply/divide unit 192. Floating point registers FLR (each with an associated tag register) can feed the RU's via an FLR bus and the FLB's can feed the RU's via an FLB bus. A common data bus CDB can be fed from the FLB's, the adder unit and the multiply/divide unit and can feed the RU's, the store data buffers 244 and the FLR's. The FLR bus can be gated (not shown) to the CDB to permit the contents of one FLR to be transferred to another. Instructions from an in struction unit called the I-box are buffered at FLOS and decoded in turn at 595 to set the tags to control data routing. When (or just before) a given block in Fig. 17A feeding the CDB or FLR bus or FLB bus needs to send data it requests a time slot on the bus and when this is granted (subject to priority ranking in the case of simultaneous requests) it applies a tag identifying itself to the bus, this tag being compared with the tags stored at all registers &e. which can be fed from the bus and which have tags set. The data is applied to the bus after the tag and is gated into each possible destination at which the tag comparison gave equality. The tag and data occupy different lines of a bus, permitting the tag of one transfer to be on a bus at the same time as the data of a previous transfer. In the case of a two-operand arithmetic instruction (for definiteness) the two operands will normally come from FLR's or one will come from an FLR and the other from an FLB (load instructions permit the FLR's to be previously loaded from memory via the FLB's), the operands being supplied to an RU associated with the adder unit or multiply/divide unit as appropriate in the way described, and the result being sent back to the or on